1. Field of the Invention
This invention relates to the fabrication of a semiconductor device. In particular, it relates to a method of making local electrical connections to such a device.
2. Description of the Related Art
As the size of microelectronic integrated semiconductor devices is increasingly reduced, the contact resistance between metallic interconnects and silicon devices becomes a relatively greater portion of the overall circuit resistance and plays a more important role in establishing its properties. As a result, decreasing contact resistance can materially enhance the device performance and reliability. A variety of approaches have been tried in order to alleviate the problems caused by relatively high contact resistance. One such approach is the salicide (self-aligned silicide) method, wherein various silicides (metal-silicon compounds having low contact resistance with silicon) are formed on the source, drain and gate electrode regions of silicon devices as part of the fabrication process of the device. For example, the silicides may be formed on the gate electrode and over the source and drain regions, immediately after the formation of the polysilicon sidewall spacers defining the gate electrode, by the deposition of various metallic species in such a fashion that the spacers themselves serve to properly align the silicide with the device. The utility of this process depends critically on the efficiency of the fabrication scheme as well as the quality of the contacts that are achieved. Needless to say, several methods have been advanced. Pfiester et al. (U.S. Pat. No. 5,405,806) teach a method for forming a metal silicide interconnect that involves the formation of a sacrificial material, such as silicon nitride, titanium nitride or tantalum nitride, which is then etched away to define a region within which the silicide is formed. Hodges (U.S. Pat. No. 5,432,129) teaches a method by which silicides such as titanium, cobalt or molybdenum are used to form a low contact resistance junction between two different silicon conductivity types, such as a p-n junction, in an integrated circuit requiring interconnects between a variety of polycrystalline silicon types. Talwar et al. (U.S. Pat. No. 5,888,888) teaches a method of forming a silicide contact region wherein an amorphous region is first formed in the silicon by ion implantation, subsequent to which a metal is made to diffuse into that region by laser irradiation. Following these processes, the region is converted to a more crystalline form by a rapid thermal annealing (RTA) process. The method of Talwar does not include the formation of a capping layer prior to the laser irradiation. However, the use of a capping layer is a novel and important part of the present invention. It plays two roles: 1. it protects the metal layer during laser annealing, thereby insuring a high quality silicide with good interfacial characteristics; 2. it permits a more careful regulation of the energy deposition produced by the laser annealing process, thereby assuring precise depth control of the underlying junction. Yu (U.S. Pat. No. 5,953,615) teaches a method of fabricating a MOSFET with deep source/drain junctions and shallow source/drain extensions. The deep junction formation is accomplished by the use of a first step which creates an amorphous region by ion implantation (the xe2x80x9cpre-amorphizingxe2x80x9d step), which has the additional advantage of allowing easier formation of silicide contacts. The method of Yu utilizes a barrier oxide that is deposited prior to the metal layer and, thereby, does not serve the same advantageous purposes as the capping layer provided by the method of the present invention. Goto et al. (U.S. Pat. No. 5,981,372) addresses the problem of removing unwanted films that remain after the formation of a silicide. For example, the formation of a titanium silicide (TiSi) also produces a layer of titanium nitride (TiN), which must be removed by various etching processes that can damage device surfaces. The method of Goto et al. teaches the formation of a conducting metal film over the metal remaining from the silicide formation. In this way, the silicide layer is protected by the silicide formation metal, allowing subsequent cleansing processes that will not damage the silicide. Thus, the method of Goto in effect uses a metal capping layer to protect a surface from cleansing processes, which is not the role of the capping layer in the present invention. Additionally, according to the practice of the method of Goto, but unlike the practice of the method of the present invention, said capping layer is allowed to remain. The method of Goto, cited above, also differs materially from the present invention in that it does not make use of ITM or laser annealing. Cheng et al. (U.S. Pat. No. 5,624,867) teach a method for forming palladium silicided shallow junctions using implant through metal/silicide technology. Ions are implanted into a palladium or palladium silicide layer over a silicon substrate. The impurities are driven into the silicon substrate during the formation or recrystallization of the palladium silicide layer and a diffusion region with a shallow junction is formed in the substrate. Laser annealing is not employed in this method to form the silicides or to drive the impurities into the silicon substrate.
As will be seen from the discussion above, the formation of silicided contact regions by methods such as the salicide method typically involve process steps such as pre-amorphizing implants (PAI) (Talwar et al.; Yu), rapid thermal annealing (RTA) using lasers or other means (Talwar et al.; Yu; Pfeister et al.; Hodges) and/or implant through metal (ITM) schemes (Cheng et al.). Rapid thermal annealing, however, produces silicides with poor uniformity and high interfacial roughness at the silicide-silicon interface. In addition, during the formation of silicides by rapid thermal annealing (RTA) there is a tendency to consume the entire junction as junction depths decrease to less than 100 nanometers, thus depleting the dopants at the junctions. These adverse effects render the junction more vulnerable to leakage and cause high contact resistance. These problems still exist with the use of a pre-amorphizing implant (PAI) or an implant through metal (ITM) scheme. Conventional ITM schemes involve the implantation of dopant ions into the metal/silicide layer, followed by a drive-in step to form shallow junctions. One issue in such ITM schemes is the confinement of dopants in the metal/silicide during the drive-in step.
The present invention addresses the problems associated with the silicidation process as practiced in the current art and as discussed above. Accordingly, it is an object of the present invention to provide a microelectronics device and a method for its fabrication, with such device having silicided contacts and superior dopant activation and dopant profile control. It is another object of the present invention to provide a method for fabricating a microelectronics device having abrupt, shallow junctions together with silicides with desired interfacial and electrical properties. These objects will be achieved through the use of ITM (implant-through-metal) and laser technology. The dopant profile can be controlled by rendering the silicon substrate amorphous to a desired depth by ion implantation so that the depth subsequently melted by the laser irradiation corresponds to the final junction depth. The extremely high ramp-up and ramp-down rate of laser annealing makes it suitable for the formation of abrupt, shallow junctions and silicides with desired interfacial and electrical properties. The laser fluence is chosen so that it is just sufficient to melt the amorphous silicon layer beneath the metal. The silicon atoms then diffuse/mix with the metal atoms to form silicides. During laser irradiation, dopant atoms are redistributed to the melt front almost instantaneously. At the same time, the silicon atoms and metal atoms are reacting at the metal-Si interface. The amorphous silicon layer then re-crystallizes from the underlying substrate at a high re-growth velocity such that the metal atoms do not diffuse through the entire depth of the melt. In this way, shallow junctions and silicides can be formed simultaneously. Hence, the shallow junction will not be completely consumed by the silicide formation.